Planar metallization interconnection is an advanced approach to power module packaging. One advantage of this approach is the ability to interconnect a large number of small devices without wirebonds. The structure consists of multiple layers of dissimilar materials including, copper, kapton, silicon, direct bonded copper (DBC) and solder die attach. When subjected to power or thermal cycling, the difference in thermal expansion of the various layers causes interlaminar stresses and risk of delamination. In particular, potential high risk regions include the interface where plated copper vias make electrical connection to the silicon semiconductor device through thin adhesion and barrier metal films, because of the large CTE difference between them. This study examines the mechanical strength of this copper-silicon interface. The delamination mechanisms of a bimaterial interface can be classified into three types: opening mode, sliding mode, and twisting mode. The first two modes are explored in this study using specially designed experiments. The third mode does not contribute to thermo-mechanical stresses at the copper-silicon interface due to surrounding mechanical constraints and is not addressed. 3D finite element analysis of this via structure is combined with the above experimental results, to qualitatively assess the thermomechanical stress margins in a typical operating environment. Identification and understanding of these failure modes and mechanisms enables to better via designs for reliable operation of planar metallization power modules.

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