Thermal vias are widely used to reduce thermal resistance of a printed circuit board (PCB). However, fine via structure becomes an obstacle to computational fluid dynamics (CFD) simulation because fine structure requires a huge number of meshes. Therefore, an efficient modeling method of thermal via structure is needed to reduce computational time. In this paper, an effect of thermal vias on reduction of thermal resistance was experimentally and numerically investigated to gather fundamental data for thermal management of electronics. We used printed circuit board models with some kind of arrangements of thermal vias. Board materials and copper dissipating pad patterns were explored as experimental parameters. Copper pipes (unfilled vias) or rods (filled vias), the diameter of which was 1.5, 3.0 and 5.0 mm, were used as thermal via. Three materials (Glass epoxy, Stainless, and Polycarbonate), thermal conductivity of which were different, were used as board materials. The experimental results showed that area of heat dissipating copper pad patterns and board materials have strong effect on the temperature rise of the heat source. On the other hand, the number of thermal vias and via shapes have no effect on the heat source temperature. Then we performed thermal network analysis to evaluate the experimental results. From the results of the thermal network analysis, it was confirmed that an effect of thermal via is saturated at certain ratio of via area.
- Electronic and Photonic Packaging Division
Thermal Resistance Measurement and Thermal Network Analysis of Printed Circuit Board With Thermal Vias
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Hatakeyama, T, Ishizuka, M, Nakagawa, S, & Takakuwa, S. "Thermal Resistance Measurement and Thermal Network Analysis of Printed Circuit Board With Thermal Vias." Proceedings of the ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems. ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 2. Portland, Oregon, USA. July 6–8, 2011. pp. 251-258. ASME. https://doi.org/10.1115/IPACK2011-52168
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