Failures in electronic packaging under thermal fatigue often result from cracking in solder joints due to creep/fatigue crack growth. A nonlinear, time-dependent finite element analysis was performed to study the effect of critical design parameters on thermal reliability of leadless chip capacitor or resistor solder joints. The shear strain range based on thermal hysteresis response was used to study the sensitivity of various parameters, such as solder stand-off height, fillet geometry, Cu-pad length, and component length and thickness. The results were used as guidelines for designing reliable solder joints. In addition, an analytical model for the solder joint assembly was derived. It can be used .as an engineering approach for rapid assessment of large numbers of design parameters. The accuracy and effectiveness of the analytical model were evaluated by comparing with finite element results.
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June 1995
Technical Papers
Evaluation of Design Parameters for Leadless Chip Resistors Solder Joints
Edward Jih,
Edward Jih
Research Laboratory, MD 2313, Ford Motor Company, Dearborn, MI 48121-2053
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Yi-Hsin Pao
Yi-Hsin Pao
Research Laboratory, MD 2313, Ford Motor Company, Dearborn, MI 48121-2053
Search for other works by this author on:
Edward Jih
Research Laboratory, MD 2313, Ford Motor Company, Dearborn, MI 48121-2053
Yi-Hsin Pao
Research Laboratory, MD 2313, Ford Motor Company, Dearborn, MI 48121-2053
J. Electron. Packag. Jun 1995, 117(2): 94-99 (6 pages)
Published Online: June 1, 1995
Article history
Received:
August 1, 1994
Revised:
March 31, 1995
Online:
November 6, 2007
Citation
Jih, E., and Pao, Y. (June 1, 1995). "Evaluation of Design Parameters for Leadless Chip Resistors Solder Joints." ASME. J. Electron. Packag. June 1995; 117(2): 94–99. https://doi.org/10.1115/1.2792087
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