In this work, thermal characteristics of a board-level chip-scale package, subjected to coupled power and thermal cycling test conditions defined by JEDEC, are investigated through the transient thermal analysis. Tabular boundary conditions are utilized to deal with time-varying thermal boundary conditions brought by thermal cycling. It is obvious from the analysis that the presence of power cycling leads to a significant deviation of the junction temperature from the thermal cycling profile. However, for components away from the die, the deviation is insignificant. Moreover, for low-power applications, temperature histories from coupled power and thermal cycling are approximately linear combinations of temperature histories from pure power cycling and the ones from pure thermal cycling.
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September 2006
Research Papers
Transient Thermal Analysis for Board-Level Chip-Scale Packages Subjected to Coupled Power and Thermal Cycling Test Conditions
Tong Hong Wang,
Tong Hong Wang
Stress-Reliability Lab,
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Rd., Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan
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Chang-Chi Lee,
Chang-Chi Lee
Thermal Lab,
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Rd., Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan
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Yi-Shao Lai,
Yi-Shao Lai
Stress-Reliability Lab,
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Rd., Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan
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Yu-Cheng Lin
Yu-Cheng Lin
Department of Engineering Science,
e-mail: yuclin@mail.ncku.edu.tw
National Cheng Kung University
, 1 Ta-Hsueh Rd., 701 Tainan, Taiwan
Search for other works by this author on:
Tong Hong Wang
Stress-Reliability Lab,
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Rd., Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan
Chang-Chi Lee
Thermal Lab,
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Rd., Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan
Yi-Shao Lai
Stress-Reliability Lab,
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Rd., Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan
Yu-Cheng Lin
Department of Engineering Science,
National Cheng Kung University
, 1 Ta-Hsueh Rd., 701 Tainan, Taiwane-mail: yuclin@mail.ncku.edu.tw
J. Electron. Packag. Sep 2006, 128(3): 281-284 (4 pages)
Published Online: October 7, 2005
Article history
Received:
July 18, 2005
Revised:
October 7, 2005
Citation
Wang, T. H., Lee, C., Lai, Y., and Lin, Y. (October 7, 2005). "Transient Thermal Analysis for Board-Level Chip-Scale Packages Subjected to Coupled Power and Thermal Cycling Test Conditions." ASME. J. Electron. Packag. September 2006; 128(3): 281–284. https://doi.org/10.1115/1.2229229
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