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Keywords: JEDEC
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Journal Articles
Publisher: ASME
Article Type: Research Papers
J. Electron. Packag. March 2012, 134(1): 011011.
Published Online: March 19, 2012
... , C. L. , and Lai , Y. S. , 2006 , “ Support Excitation Scheme for Transient Analysis of JEDEC Board-Level Drop Test ,” J. Microelectron. Reliab. , 46 , pp. 626 – 636 . 10.1016/j.microrel.2004.12.021 13 Lai , Y. S. , Yang , P. C. , and Yeh , C. L. , 2008 , “ Effects...
Journal Articles
Publisher: ASME
Article Type: Technical Briefs
J. Electron. Packag. March 2007, 129(1): 105–108.
Published Online: June 6, 2006
... reliability JEDEC The wafer-level chip-scale package (WLCSP) contains a bare die, whose electrical signals pass directly from the die via solder joints to the printed circuit board (PCB). In this way, the dimension of WLCSP is virtually that of the die. Nevertheless, due to considerable thermal...
Journal Articles
Publisher: ASME
Article Type: Research Papers
J. Electron. Packag. September 2006, 128(3): 281–284.
Published Online: October 7, 2005
...Tong Hong Wang; Chang-Chi Lee; Yi-Shao Lai; Yu-Cheng Lin In this work, thermal characteristics of a board-level chip-scale package, subjected to coupled power and thermal cycling test conditions defined by JEDEC, are investigated through the transient thermal analysis. Tabular boundary conditions...